Electronic matrix arrays find considerable application in image sensors (e.g. X-ray image sensors) and active matrix liquid crystal displays (AMLCDs). Such devices generally include X and Y (or row and column) address lines which are horizontally and vertically spaced apart and cross at an angle to one another thereby forming a plurality of crossover points. Associated with each crossover point is an element (e.g. pixel) to be selectively addressed. These elements in liquid crystal displays are liquid crystal inclusive pixels, while in image sensors these elements are storage capacitors or phtotdiodes. Arrays of these elements are formed on a substrate in both LCDs and image sensors. See, for example, U.S. Pat. Nos. 5,641,974 and 4,728,802 the disclosures of which are hereby incorporated herein by reference.
Typically, a switching or isolation device such as a diode or thin-film transistor (TFT) is associated with each array element. The isolation devices permit the individual elements to be selectively addressed by the application of suitable potentials between respective pairs of the X and Y address lines. Thus, the diodes or TFTs act as switching elements for energizing or otherwise addressing corresponding pixel electrodes in LCD applications, and for addressing storage capacitors or phtotdiodes in imager applications.
The use of PIN (same as NIP) diodes is known. For example, see U.S. Pat. Nos. 4,728,802 and 4,868,616, the disclosures of which is incorporated herein by reference, in which PIN diodes are provided in each of an imager and a liquid crystal display, respectively. However, it is very difficult to control leakage current of PIN diodes and difficult to obtain a robust silicon (Si) etching process with known a-Si (amorphous silicon) based n+/i/p+ PIN/NIP diodes.
Prior art FIGS. 1 and 2 disclose a known method for making PIN diodes in a sensor application. As shown in FIG. 1, substrate 1 is provided. Then, bottom diode metal 3 is deposited on substrate 1. This bottom metal 3 is then patterned and etched to form the two portions 3 illustrated in FIGS. 1 and 2. Thereafter, the n+, intrinsic (i), and p+ a-Si layers are deposited over portions 3 on substrate 1. Prior to patterning or etching these semiconductor layers, an indium-tin-oxide (ITO) layer is deposited over the p+ layer. After these semiconductor and ITO layers are deposited, they are patterned and etched to form the two diodes illustrated in FIG. 2. The ITO is first patterned and etched, and thereafter the silicon PIN layers are dry etched. The result is the FIG. 2 structure including switching PIN diode 5 and light sensitive photodiode 7.
As shown in FIG. 2, switching diode 5 includes bottom metal electrode 3, n+ a-Si layer 9, intrinsic a-Si layer 11, p+ a-Si layer 13, and overlying ITO top electrode layer 15. Photodiode 7 includes each of these same layers deposited over larger metal layer portion 3. The image sensor of FIG. 2 functions in a known manner.
Unfortunately, the FIGS. 1-2 method/structure suffers from a number of problems, three of which are described below. First, because silicon (PIN material) is etched in either Cl and/or F based plasmas, which have poor etch selectivity with regard to metals such as Mo, Ti, Ta, and the like, this limits the number of metals which may be used as bottom electrode layer 3. This problem limits the instant applicants to the use of Cr for bottom metal electrode layer 3. This, of course, is undesirable.
Second, when CF.sub.4, CHF.sub.3 based plasmas are used for etching Si, PIN (or NIP) diodes tend to leave polymer residue film on diode sidewalls and glass substrate, and thus post-RIE (reactive ion etching) chemical treatment is typically needed to clean the sidewall(s) of the diodes and glass substrate. This of course is undesirable, as post-RIE treatments are expensive, and difficult to perform satisfactorily.
Third, when Cl.sub.2 plasma is used to etch the silicon, low leakage current may be obtained. However, unfortunately the RIE process chamber becomes severely contaminated by non-volatile metal chloride generated during the overetch process. This contamination is seen in cases of Mo, Cr, and Ta when used as the bottom metal electrode layer 3. Such contamination can slow the etch rate and induce non-uniformities and therefore increases downtime of the manufacturing process, and leads to increased costs.
It is apparent from the above that there exists a need in the art for an improved PIN diode design, and method of manufacturing same, which (i) results in PIN diodes having low leakage current characteristics; (ii) enables a large variety of metals such as Mo, Ti, Ta, and the like to be used as the bottom electrode layer in the PIN diode; (iii) eliminates the need for Cr target installation and Cr etching development in a wet bench; (iv) substantially reduces chamber contamination and thus improves machine uptime; (v) eliminates post RIE treatment processes; and/or (vi) results in better crossover yield because there will be two insulating layers (e.g. silicon nitride layers) between column and row lines.
It is a purpose of this invention to fulfill the above-described needs in the art, as well as other needs which will become apparent to the skilled artisan from the following detailed description of this invention.